Nonvolatile Memory Devices And Methods Of Fabricating The Same

ABSTRACT

Nonvolatile memory devices including a first interlayer insulating film and a second interlayer insulating film separated from each other and are stacked sequentially, a first electrode penetrating the first interlayer insulating film and the second interlayer insulating film, a resistance change film along a top surface of the first interlayer insulating film, side surfaces of the first electrode, and a bottom surface of the second interlayer insulating film, and a second electrode between the first interlayer insulating film and the second interlayer insulating film.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2011-0044612, filed on May 12, 2011 in the KoreanIntellectual Property Office (KIPO), the entire contents of which isincorporated herein by reference.

BACKGROUND

1. Field

Example embodiments of the inventive concepts relate to nonvolatilememory devices and methods of fabricating the same.

2. Description of the Related Art

Semiconductor memory devices are memory devices implemented using asemiconductor, such as Si, Ge, GaAs, or InP. Semiconductor memorydevices are classified as volatile memory devices or nonvolatile memorydevices.

The volatile memory devices lose stored data when the power supply isinterrupted. Examples of the volatile memory devices include staticrandom access memories (SRAMs), dynamic random access memories (DRAMs),and synchronous dynamic random access memories (SDRAM). The nonvolatilememory devices retain stored date even when the power supply isinterrupted. Examples of the nonvolatile memory devices includeread-only memories (ROM), programmable read-only memories (PROMs),erasable programmable read-only memories (EPROMs), electrically erasableprogrammable read-only memories (EEPROMs), flash memories, and resistivememories (e.g., phase-change random access memories (PRAMs),ferroelectric random access memories (FRAM), and resistive random accessmemories (RRAM)).

SUMMARY

Example embodiments of the inventive concepts may provide resistivememory devices with increased integration density and methods offabricating resistive memory devices with increased integration density.

According to example embodiments of the inventive concepts, anonvolatile memory device includes a first interlayer insulating filmand a second interlayer insulating film which are separated from eachother and are stacked sequentially, a first electrode which penetratesthe first interlayer insulating film and the second interlayerinsulating film, a resistance change film which is formed along a topsurface of the first interlayer insulating film, side surfaces of thefirst electrode, and a bottom surface of the second interlayerinsulating film, and a second electrode which is formed between thefirst interlayer insulating film and the second interlayer insulatingfilm.

According to other example embodiments of the inventive concepts, anonvolatile memory device includes a substrate, a plurality ofinterlayer insulating films which are stacked sequentially on thesubstrate and are separated from each other, a plurality of firstelectrodes which penetrate the interlayer insulating films, a pluralityof second electrodes, each of which is formed between every two adjacentones of the stacked interlayer insulating films and which are separatedfrom the first electrodes, and a plurality of resistance change filmswhich are interposed between the first electrodes and the secondelectrodes, respectively.

According to at least one example embodiment, a nonvolatile memorydevice includes a first interlayer insulating film, a second interlayerinsulating film stacked on the first interlayer insulating film, thefirst and second interlayer insulating films separated from each other,a first electrode penetrating through the first interlayer insulatingfilm and the second interlayer insulating film, a resistance change filmon a top surface of the first interlayer insulating film, a side surfaceof the first electrode, and a bottom surface of the second interlayerinsulating film and a second electrode between the first interlayerinsulating film and the second interlayer insulating film.

According to at least one example embodiment, a nonvolatile memorydevice includes a substrate layer, a plurality of interlayer insulatingfilms stacked on the substrate layer, the interlayer insulating filmsseparated from each other, a plurality of first electrodes penetratingthe interlayer insulating films, a plurality of second electrodes, eachof the second electrodes between a different adjacent pair of theinterlayer insulating films and separated from the first electrodes, anda plurality of resistance change films between the first electrodes andthe second electrodes.

According to at least one example embodiment, a semiconductor deviceincludes a conductive pillar, at least three electrodes spaced apart onthe conductive pillar, a plurality of insulating layers on theconductive pillar, each of the insulating layers separating a differentpair of the electrodes and a variable resistance layer extending in alengthwise direction of the pillar, the variable resistance layerseparating the conductive pillar from each of the electrodes, each ofthe plurality of insulating layers separating the conductive pillar fromthe variable resistance layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the followingbrief description taken in conjunction with the accompanying drawings.FIGS. 1-18 represent non-limiting, example embodiments as describedherein.

FIG. 1 is a perspective block diagram illustrating resistive memorydevices according to example embodiments;

FIG. 2 is a perspective diagram illustrating a memory block of FIG. 1;

FIG. 3 is a cross-sectional view taken along the line III-III′ of FIG.2;

FIG. 4 is an enlarged cross-sectional diagram illustrating a region TS1of FIG. 3;

FIG. 5 is an enlarged cross-sectional diagram illustrating resistivememory devices according to other example embodiments;

FIG. 6 is a cross-sectional diagram illustrating resistive memorydevices according to still other example embodiments;

FIG. 7 is an enlarged cross-sectional diagram illustrating a region TS3of FIG. 6;

FIG. 8 is an enlarged cross-sectional diagram illustrating resistivememory devices according to further example embodiments;

FIGS. 9-14 are cross-sectional diagrams illustrating intermediateprocesses in at least one method of fabricating resistive memory devicesof FIG. 1;

FIG. 15 is a diagram illustrating an intermediate process in at leastone method of fabricating resistive memory devices of FIG. 6;

FIG. 16 is a block diagram illustrating memory systems according to someexample embodiments;

FIG. 17 is a block diagram illustrating example applications of thememory systems shown in FIG. 16; and

FIG. 18 is a block diagram illustrating computing systems includingmemory systems of FIG. 17.

It should be noted that these figures are intended to illustrate thegeneral characteristics of methods, structure and/or materials utilizedin certain example embodiments and to supplement the written descriptionprovided below. These drawings are not, however, to scale and may notprecisely reflect the precise structural or performance characteristicsof any given embodiment, and should not be interpreted as defining orlimiting the range of values or properties encompassed by exampleembodiments. For example, the relative thicknesses and positioning ofmolecules, layers, regions and/or structural elements may be reduced orexaggerated for clarity. The use of similar or identical referencenumbers in the various drawings is intended to indicate the presence ofa similar or identical element or feature.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference tothe accompanying drawings, in which example embodiments are shown.Example embodiments may, however, be embodied in many different formsand should not be construed as being limited to the embodiments setforth herein; rather, these embodiments are provided so that thisdisclosure will be thorough and complete, and will fully convey theconcept of example embodiments to those of ordinary skill in the art. Inthe drawings, the thicknesses of layers and regions are exaggerated forclarity. Like reference numerals in the drawings denote like elements,and thus their description will be omitted.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Like numbers indicate like elementsthroughout. As used herein the term “and/or” includes any and allcombinations of one or more of the associated listed items. Other wordsused to describe the relationship between elements or layers should beinterpreted in a like fashion (e.g., “between” versus “directlybetween,” “adjacent” versus “directly adjacent,” “on” versus “directlyon”).

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises”, “comprising”, “includes” and/or “including,” if usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of exampleembodiments. As such, variations from the shapes of the illustrations asa result, for example, of manufacturing techniques and/or tolerances,are to be expected. Thus, example embodiments should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle may have rounded or curved features and/or a gradient ofimplant concentration at its edges rather than a binary change fromimplanted to non-implanted region. Likewise, a buried region formed byimplantation may result in some implantation in the region between theburied region and the surface through which the implantation takesplace. Thus, the regions illustrated in the figures are schematic innature and their shapes are not intended to illustrate the actual shapeof a region of a device and are not intended to limit the scope ofexample embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined incommonly-used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

FIG. 1 is a perspective block diagram illustrating resistive memorydevices according to example embodiments. FIG. 2 is a perspectivediagram illustrating a memory block of FIG. 1. FIG. 3 is across-sectional view taken along the line III-III′ of FIG. 2. FIG. 4 isan enlarged cross-sectional diagram illustrating a region TS1 of FIG. 3.Referring to FIG. 1, a memory cell array of a resistive memory device 1according to at least one example embodiment may include a plurality ofmemory blocks BLK1-BLKn, where n is a natural number. Each of the memoryblocks BLK1-BLKn may extend in first through third directions D1-D3. Asillustrated in FIG. 1, the first through third directions D1-D3 may bedirections that intersect each other and are different from each other.For example, the first through third directions D1-D3 may be, but arenot limited to, directions that intersect each other at right angles.

Referring to FIGS. 2-4, a memory block BLKi (1≦i≦n, where i is a naturalnumber) may include a plurality of interlayer insulating films 112, aplurality of first electrodes 115, a plurality of second electrodes211-291 (e.g., 211, 221, 231, 241, 251, 261, 271, 281 and 291), 212-292(e.g., 212, 222, 232, 242, 252, 262, 272, 282 and 292) and 213-293(e.g., 213, 223, 243, 253, 263, 273, 283 and 293), and a plurality ofresistance change films 116 on a substrate 111. The interlayerinsulating films 112 may be separated from each other in the seconddirection D2 and may be sequentially stacked on the semiconductorsubstrate 111 in the second direction D2. As illustrated in FIG. 2, eachof the interlayer insulating films 112 may extend in the first directionD1.

The first electrodes 115 may extend in the second direction D2, and thesecond electrodes 211-291, 212-292 and 213-293 may extend in the firstdirection D1. The first electrodes 115 may be on the substrate 111 inthe form of pillars and may penetrate the stacked interlayer insulatingfilms 112. Each of the second electrodes 211-291, 212-292 and 213-293may be between a different pair of adjacent stacked interlayerinsulating films 112. The second electrodes 211-291, 212-292 and 213-293may be separated from the first electrodes 115 and may intersect thefirst electrodes 115. First electrodes spaced in the direction D3 may beconnected by one of bit lines 331-333 through connection pads and/orplugs 320.

The first electrodes 115 may be, but are not limited to, Ru, RuOx,Ti/TiN, Zr/TiN, NiSix, TiN, Wn, W, Al, Cu, and/or an alloy of thesematerials. The second electrodes 211-291, 212-292 and 213-293 may be,but are not limited to, Ti/TiN, Ta/TiN, W, Pt, Pd, Rh, Ru, Ir and/or analloy of these materials. The resistance change films 116 may be betweenthe first electrodes 115 and the second electrodes 211-291, 212-292 and213-293. The resistance change films 116 may extend in the firstdirection D1. The resistance change films 116 may be formed in a zigzagshape in the second direction D2. In each region in which one of thefirst electrodes 115 intersect one of the second electrodes 211-291,212-292 and 213-293 there may be a resistive memory cell TS1.

Each of the resistance change films 116 may be along a top surface (see116 a in FIG. 4) of an interlayer insulating film 112, side surfaces(see 116 b in FIG. 4) of a first electrode 115, and a bottom surface(see 116 c in FIG. 4) of another interlayer insulating film 112, and/ora different portion of an interlayer insulating film 112. The resistancechange films 116 may be conforming or conformal to the shapes of theinterlayer insulating films 112 and the first electrodes 115. Each ofthe second electrodes 211-291, 212-292 and 213-293 may fill a spacebetween an interlayer insulating film 112 that may be disposedthereunder and another interlayer insulating film 112 that may bedisposed thereon. The resistance change films 116 may be, for example, atransition metal oxide (TMO). For example, the resistance change films116 may be, but are not limited to, HfOx, TiOx, TaOx, ZnO, Ti₂O, Nb₂O₅,ZrO₂ and/or NiO.

Referring to FIGS. 2 and 3, the first electrodes 115 may be separated inthe first direction D1 and the third direction D3. The first electrodes115 may be arranged in a matrix. In the drawings, the first electrodes115 may be arranged in a 3×3 matrix. However, example embodiments of theinventive concepts are not limited thereto. A trench T may be in theinterlayer insulating films 112 between every two adjacent firstelectrodes 115 arranged in the third direction D3. The first electrodes115 arranged in the third direction D3 may be electrically connected toeach other by bit lines 331-333. The first electrodes 115 that may bearranged in the first direction D1 may be electrically connected to eachother by the resistance change films 116 that may extend in the firstdirection D1.

FIG. 5 is an enlarged cross-sectional diagram illustrating resistivememory devices 3 according to other example embodiments. The followingdescription may describe differences from the resistive memory device 1and description of like elements may be omitted. Referring to FIG. 5, aresistive memory cell TS2 in a resistive memory device 2 according to atleast one example embodiment may further include a two-way diode 119that may be between a first electrode 115 and a second electrode (e.g.,233). The two-way diode 119 may be, for example, VO₂. The two-way diode119 may be along a top surface of an interlayer insulating film 112,side surfaces of the first electrode 115 and a bottom surface of anotherinterlayer insulating film 112. The two-way diode 119 may be between aresistance change film 116 and the second electrode 233. However,example embodiments are not limited thereto. For example, according toat least one example embodiment the two-way diode 119 may be between thefirst electrode 115 and the resistance change film 116.

FIG. 6 is a cross-sectional diagram illustrating resistive memorydevices 3 according to still other example embodiments. FIG. 7 is anenlarged cross-sectional diagram illustrating a region TS3 of FIG. 6.The following description may describe differences from the resistivememory device 1 and description of like elements may be omitted.Referring to FIGS. 6 and 7, each side surface of each of firstelectrodes 115 in the resistive memory device 3 according to exampleembodiments may include a plurality of grooves H. Each of the grooves Hmay be between an interlayer insulating film 112 that may be thereon andanother interlayer insulating film 112 that may be thereunder. Aresistance change film 116 may be along the grooves H of each sidesurface of each of the first electrodes 115. Surfaces of the resistancechange film(s) 116 between one of the first electrodes 115 and eachgroup of second electrodes 211-291, 212-292 and/or 213-293 may be curvedsurfaces (e.g., curved surfaces R). When a bias is applied to one of thefirst electrodes 115 and at least one of the second electrodes 211-291,212-292 and 213-293, an electric field may not be concentrated in acertain area. The electric field may be evenly distributed over anentire curved surface R of the resistance change film 116. Filaments maybe evenly induced over the entire curved surface R of the resistancechange film 116. Filaments may be prevented and/or reduced in unwantedareas of the resistance change film 116 and with a uniformity of thefilaments may be increased.

FIG. 8 is an enlarged cross-sectional diagram illustrating resistivememory devices 4 according to further example embodiments. The followingdescription may describe differences from the resistive memory device 3and description of like elements may be omitted. Referring to FIG. 8, aresistive memory cell TS4 in a resistive memory device 4 according toexample embodiments may include a two-way diode 119 between a firstelectrode 115 and a second electrode (e.g., 233). The two-way diode 119may be along a top surface of an interlayer insulating film 112, sidesurfaces of the first electrode 115, and a bottom surface of anotherinterlayer insulating film 112. In FIG. 8, the two-way diode 119 may bebetween a resistance change film 116 and a second electrode 233.However, example embodiments are not limited thereto. For example, thetwo-way diode 119 may be between the first electrode 115 and theresistance change film 116 and/or between the resistance change film 116and the second electrode 233.

FIGS. 9-14 are cross-sectional diagrams illustrating intermediateprocesses in at least one method of fabricating a resistive memorydevice 1 of FIG. 1. Referring to FIG. 9, a plurality of sacrificialfilms 199 and a plurality of interlayer insulating films 112 may bestacked alternately. The sacrificial films 199 and the interlayerinsulating films 112 may be materials with different etch rates. Forexample, the sacrificial films 199 may be nitride films, and theinterlayer insulating films 112 may be oxide films. Referring to FIG.10, a plurality of first electrodes 115 may be formed in the shape ofpillars to penetrate the sacrificial films 199 and the interlayerinsulating films 112. Through holes may penetrate the sacrificial films199 and the interlayer insulating films 112 may be formed by, forexample, anisotropic etching. The through holes may be filled (e.g.,completely filled) with a first electrode material using, for example,chemical vapor deposition (CVD), physical vapor deposition (PVD) and/oratomic layer deposition (ALD). The first electrode material may be, butis not limited to, Ru, RuOx, Ti/TiN, Zr/TiN, NiSix, TiN, Wn, W, Al, Cuand/or an alloy of these materials.

Referring to FIGS. 11 and 12, regions of each side surface of each ofthe first electrodes 115 may be exposed by removing the sacrificialfilms 199. The sacrificial films 199 and part of the interlayerinsulating films 112 may be removed to form a trench T which may beseparated from each of the first electrodes 115 as illustrated in FIG.11. A trench T may be formed between every two adjacent first electrodes115. The sacrificial films 199 may be removed by, for example, wetetching as illustrated in FIG. 12. The process of removing thesacrificial films 199 may be referred to as a pull-back process. Thepull-back process may use, for example, phosphoric acid, sulfuric acid,hydrochloric acid and/or a mixture of these solutions.

Referring to FIGS. 13 and 14, a plurality of resistance change films 116may be formed along top and bottom surfaces of the interlayer insulatingfilms 112 and the exposed regions of the side surfaces of the firstelectrodes 115. A resistance change material and a conductive material299 may be sequentially formed as illustrated in FIG. 13. Part of theconductive material 299 may be removed to complete each group of secondelectrodes 211-291, 212-292 and/or 213-293 which may be separated fromeach other by the interlayer insulating films 112, as illustrated inFIG. 14.

The forming of the resistance change films 116 and the forming of thesecond electrodes 211-291, 212-292 and 213-293 (the forming of theconductive material 299 for forming the second electrodes 211-291,212-292 and 213-293) may include using an in-situ method. The forming ofthe resistance change films 116 and the forming of the second electrodes211-291, 212-292 and 213-293 may use, for example, ALD and/or CVD.However, example embodiments are not limited thereto. The resistancechange films 116 may be, for example a TMO. The resistance change films116 may be, but are not limited to, HfOx, TiOx, TaOx, ZnO, Ti₂O, Nb₂O₅,ZrO₂ and/or NiO. The second electrodes 211-291, 212-292 and 213-293 maybe, but are not be limited to, Ti/TiN, Ta/TiN, W, Pt, Pd, Rh, Ru, Ir,and/or an alloy of these materials.

FIG. 15 is a diagram illustrating an intermediate process in at leastone method of fabricating a resistive memory device 3 of FIG. 6. Methodof fabricating the resistive memory device 3 according to exampleembodiments may be similar to methods of fabricating the resistivememory device 1 according to example embodiments. Therefore, descriptionof the same or similar processes may be omitted. A method of fabricatingthe resistive memory device 3 according to example embodiments mayfurther include a process of FIG. 15 between the process (the removingof sacrificial films) of FIG. 12 and the process (the forming of aresistance change material and a conductive material) of FIG. 13.

Referring to FIG. 15, grooves H may be formed in regions of sidesurfaces of each first electrode 115 which may be exposed between pairsof interlayer insulating films 112. For example, wet etch and/or dryetch may be performed using an etch selectivity between the interlayerinsulating films 112 and the first electrodes 115, thereby forming thegrooves H. A dry etch process may use at least one of Cl₂, NH₃ and/orCCl₄.

FIG. 16 is a block diagram illustrating memory systems according to someexample embodiments. Referring to FIG. 16, a memory system 1000 mayinclude a nonvolatile memory device 1100 and a controller 1200. Thenonvolatile memory device 1100 may be one of the memory devicesdescribed above with reference to FIGS. 1-8. The controller 1200 may beconnected to a host HOST and the nonvolatile memory device 1100. Thecontroller 1200 may be configured to access the nonvolatile memorydevice 1100 in response to a request from the host. For example, thecontroller 1200 may be configured to control read/write/erase/backgroundoperations of the nonvolatile memory device 1100. The controller 1200may be configured to provide an interface between the nonvolatile memorydevice 1100 and the host HOST. The controller 1200 may be configured todrive firmware for controlling the nonvolatile memory device 1100.

The controller 1200 may include well-known components, for example, arandom access memory (RAM), a processing unit, a host interface and/or amemory interface. The RAM may be used as at least one of a workingmemory of the processing unit, a cache memory between the nonvolatilememory device 1100 and the host, and a buffer memory between thenonvolatile memory device 1100 and the host. The processing unit maycontrol the overall operation of the controller 1200. The host interfacemay include a protocol for data exchange between the host HOST and thecontroller 1200. For example, the controller 1200 may be configured tocommunicate with an external device (e.g., the host HOST) using at leastone of various interface protocols.

The interface protocols may include, for example, a universal serial bus(USB) protocol, a multimedia card (MMC) protocol, a peripheral componentinterconnection (PCI) protocol, a PCI-express (PCI-E) protocol, anadvanced technology attachment (ATA) protocol, a serial-ATA protocol, aparallel-ATA protocol, a small computer small interface (SCSI) protocol,an enhanced small disk interface (ESDI) protocol and/or an integrateddrive electronics (IDE) protocol. The memory interface may interfacewith the nonvolatile memory device 1100. For example, the memoryinterface may include a NAND interface and/or a NOR interface.

The memory system 1000 may further include an error correction block(not shown). The error correction block may be configured to detect andcorrect an error in data read from the nonvolatile memory device 1100 byusing an error correction code (ECC). For example, the error correctionblock may be provided as a component of the controller 1200. The errorcorrection block may also be provided as a component of the nonvolatilememory device 1100. The controller 1200 and the nonvolatile memorydevice 1100 may be integrated into one semiconductor device. As anexample, the controller 1200 and the nonvolatile memory device 1100 maybe integrated into one semiconductor device as a memory card. Forexample, the controller 1200 and the nonvolatile memory device 1100 maybe integrated into one semiconductor device as a personal computer (PC)card (e.g., Personal Computer Memory Card International Association(PCMCIA)), a compact flash card (CF), a smart media card (SM/SMC), amemory stick, a multimedia card (e.g., MMC, RS-MMC and MMCmicro), a SDcard (e.g., SD, miniSD, microSD, and SDHC), and/or a universal flashstorage (UFS).

As another example, the controller 1200 and the nonvolatile memorydevice 1100 may be integrated into one semiconductor device as a solidstate drive (SSD). The SSD may include a storage device which may storedata in a semiconductor memory. When the memory system 1000 may be usedas an SSD, the operation speed of the host connected to the memorysystem 1000 may increase significantly.

The memory system 1000 may be applicable to computers, ultra-mobile PCs(UMPCs), workstations, net-books, personal digital assistants (PDAs),portable computers, web tablets, wireless phones, mobile phones, smartphones, e-books, portable multimedia players (PMPs), portable gamedevices, navigation devices, black boxes, digital cameras,three-dimensional televisions, digital audio recorders, digital audioplayers, digital picture recorders, digital picture players, digitalvideo recorders, digital video players, devices capable oftransmitting/receiving information in wireless environments, one ofvarious electronic devices constituting a home network, one of variouselectronic devices constituting a computer network, one of variouselectronic devices constituting a telematics network, a radio frequencyidentification (RFID) device and/or various components constituting acomputing system.

The nonvolatile memory device 1100 and/or the memory system 1000 may bemounted in various types of packages. Examples of packages that mayinclude the nonvolatile memory device 1100 and/or the memory system 1000include Package on Package (PoP), Ball Grid Arrays (BGAs), Chip ScalePackages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic DualIn-line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip OnBoard (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric QuadFlat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline IntegratedCircuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small OutlinePackage (TSOP), System In Package (SIP), Multi Chip Package (MCP),Wafer-level Fabricated Package (WFP), and/or Wafer-level Processed StackPackage (WSP).

FIG. 17 is a block diagram illustrating example applications of thememory systems shown in FIG. 16. Referring to FIG. 17, a memory system2000 may include a nonvolatile memory device 2100 and a controller 2200.The nonvolatile memory device 2100 may include a plurality ofnonvolatile memory chips. The nonvolatile memory chips may form multiplememory chip groups. Each of the memory chip groups may have a commonchannel for communication with the controller 2200. For example, thenonvolatile memory chips may communicate with the controller 2200through first through k^(th) channels CH1-CHk. Each of the nonvolatilememory chips may include at least one of the nonvolatile memory devices1-4 described above with reference to FIGS. 1-8. A plurality ofnonvolatile memory chips may be connected to one channel. However, thememory system 2000 may be modified, for example, such that onenonvolatile memory chip may be connected to one channel.

FIG. 18 is a block diagram illustrating computing systems including amemory system of FIG. 17. Referring to FIG. 18, a computing system 3000may include a central processing unit (CPU) 3100, a RAM 3200, a userinterface 3300, a power supply 3400 and a memory system 2000. The memorysystem 2000 may be electrically connected through a system bus 3500 tothe CPU 3100, the RAM 3200, the user interface 3300 and the power supply3400. Data, which may be provided through the user interface 3300 and/orprocessed by the CPU 3100, may be stored in the memory system 2000. Thenonvolatile memory device 2100 may be connected to the system bus 3500through the controller 2200. However, the nonvolatile memory device 2100may also, for example, be connected directly to the system bus 3500.

In FIG. 18, the memory system 2000 described above with reference toFIG. 17 is provided. However, the memory system 2000 may be replaced by,for example, the memory system 1000 described above with reference toFIG. 16. The computing system 3000 may also include each of the memorysystems 1000 and 2000 described above with reference to FIGS. 16 and 17.

While example embodiments have been particularly shown and described, itwill be understood by one of ordinary skill in the art that variationsin form and detail may be made therein without departing from the spiritand scope of the claims.

1. A nonvolatile memory device, comprising: a first interlayerinsulating film; a second interlayer insulating film stacked on thefirst interlayer insulating film, the first and second interlayerinsulating films separated from each other; a first electrodepenetrating through the first interlayer insulating film and the secondinterlayer insulating film; a resistance change film on a top surface ofthe first interlayer insulating film, a side surface of the firstelectrode, and a bottom surface of the second interlayer insulatingfilm; and a second electrode between the first interlayer insulatingfilm and the second interlayer insulating film.
 2. The memory device ofclaim 1, wherein the side surface of the first electrode is grooved, thegroove extending between the first interlayer insulating film and thesecond interlayer insulating film, and the resistance change film is onthe side surface of the first electrode in the groove.
 3. The memorydevice of claim 2, wherein the side surface of the first electrode inthe groove is curved.
 4. The memory device of claim 1, wherein thesecond electrode includes a top surface, a bottom surface and sidesurfaces, and the resistance change film is on the top and bottomsurfaces of the second electrode, and on part of the side surfaces ofthe second electrode.
 5. The memory device of claim 1, furthercomprising: a two-way diode between the first electrode and the secondelectrode, the diode on the top surface of the first interlayerinsulating film, the side surface of the first electrode, and the bottomsurface of the second interlayer insulating film.
 6. The memory deviceof claim 1, wherein the resistance change film is a transition metaloxide (TMO).
 7. A nonvolatile memory device, comprising: a substratelayer; a plurality of interlayer insulating films stacked on thesubstrate layer, the interlayer insulating films separated from eachother; a plurality of first electrodes penetrating the interlayerinsulating films; a plurality of second electrodes, each of the secondelectrodes between a different adjacent pair of the interlayerinsulating films and separated from the first electrodes; and aplurality of resistance change films between the first electrodes andthe second electrodes.
 8. The memory device of claim 7, wherein each ofthe resistance change films is on top and bottom surfaces of theinterlayer insulating films and on side surfaces of one of the firstelectrodes.
 9. The memory device of claim 8, wherein each of the secondelectrodes includes a top surface, a bottom surface and side surfaces,and each of the resistance change films surrounds the top and bottomsurfaces of the second electrodes and part of side surfaces of thesecond electrodes.
 10. The memory device of claim 7, wherein a sidesurface of each of the first electrodes includes a plurality of groovesbetween the interlayer insulating films, and the resistance change filmsare on the first electrodes in the grooves.
 11. The memory device ofclaim 10, wherein the surfaces of the first electrodes in the groovesare curved.
 12. The memory device of claim 7, further comprising: atrench in the interlayer insulating films extending between everyadjacent pair of the first electrodes, wherein the first electrodes arearranged in first and second directions parallel to the substrate layer,the pairs are arranged in the first direction, and the trenches extendin the second direction.
 13. The memory device of claim 12, wherein thefirst electrodes are arranged in rows in the first direction, and thefirst electrodes in one row are electrically connected to each other bya bit line.
 14. The memory device of claim 12, wherein the firstelectrodes are arranged in columns in the second direction, and thefirst electrodes in one column are electrically connected to each otherby at least one of the resistance change films.
 15. The memory device ofclaim 7, further comprising: a plurality of two-way diodes between thefirst electrodes and the second electrodes, the diodes on top and bottomsurfaces of the interlayer insulating films and side surfaces of thefirst electrodes.
 16. A vertical semiconductor device, comprising: aconductive pillar; at least three electrodes spaced apart on theconductive pillar; a plurality of insulating layers on the conductivepillar, each of the insulating layers separating a different pair of theelectrodes; and a variable resistance layer extending in a lengthwisedirection of the pillar, the variable resistance layer separating theconductive pillar from each of the electrodes, each of the plurality ofinsulating layers separating the conductive pillar from the variableresistance layer.
 17. The vertical semiconductor device of claim 16,wherein the variable resistance layer separates the electrodes from theinsulating layers.
 18. The vertical semiconductor device of claim 17,further comprising: a diode layer; wherein portions of the variableresistance layer separating the conductive pillar from the electrodesare one of in direct contact with the conductive pillar and separatedfrom the conductive pillar by the diode layer, and each of theinsulating layers separates the diode layer from the conductive pillar.19. The vertical semiconductor device of claim 18, wherein a surface ofthe conductive pillar between each pair of insulating layers is concave.20. A memory system, comprising: a controller; and the nonvolatilememory device of claim
 1. 21-22. (canceled)